13 March 2025
I’ve been thinking about some of my other assumptions with regard to these little chips and what it takes to program them. One thing is that I had been laboring under the false assumption that the interrupt vector table, should one decide to use one, must reside at location zero in the program memory. In truth, I understood that it could be located on any 1 KB boundary, and you can (must) tell it where by writing to the mtvec CSR. Per the QingKe V2 Processor Manual, Section 2,2 Exception, p. 4:
"It should be noted that the vector table base address needs to be 1KB aligned in the QingKe V2 microprocessor."This limitation is not present on the other QingKe processor families.
So for a chip with a mighty expanse of 16 KB, you actually have 16 different choices available to you. One of the good reasons to stick the vector table at address zero is that it avoids any gaps in the program memory when you’re writing really small applications, as I tend to do with these chips. It totally doesn’t matter if you spread your ones and zeros across the entire continuum of available sites or cram them all at one end or the other.
Additionally, you could even point the mtvec CSR at one of two SRAM addresses, 0x20000000 or 0x20000400, and have an instantly reconfigurable vector table in volatile memory. I have no idea if this would actually work or not. You could even use the VTF mechanism to cover any interrupt requirements in the device set-up stage, as long as you only need two of them. The bigger chips offer four VTF slots.
I really need to design some new PCBs for all the incoming chips. One thing I noticed about the new CH32V002 parts was what looks like a ground pad on the bottom of the SOP8 package, the J4M6 variant. This appears to be an anomaly as the data sheet makes no mention of it. Additionally, the “photo” of the TSSOP20 package just has the identifier “813524E47” on it, and no part number or WCH logo, so these may just be placeholder photos until they can book some studio time for a proper photo-shoot.
I also see that there is supposed to be a QFN12 package with 11 available IO lines, the -D4U6 variant. What sorcery is this? It’s 2mm square. So tiny! I can’t wait to make some eensy weensy doo-dads with these little chips.
Other differences of note when compared to the original CH32V003:
12 bit ADC, 3 MS/sec sampling rate
8 channel Touch-Key channel detection
RV23EmC - hardware multiplication
4 KB SRAM
2.0-5.5 VDC system power supply
2 ms power on resetStill no SPI on the SOP8 or the QFN12 packages. It’s not like I’m invested in understanding the SPI peripheral on this chip or anything…
As the SOP8 package still has both dedicated VSS and VDD pins, I can design a PCB that omits the solder pad, if it even really has one. I don’t expect to see the chips in person for at least another week.
The CH32V006 also have some upgrades when compared to the CH32V003 or -002:
62 KB flash
8 KB SRAM
2 USARTs
31 GPIO lines
GPIOA PA0-PA7
GPIOB PB0-PB6
GPIOC PC0-PC7
GPIOD PD0-PD7
Operational amplifier
3 timers, 2 watch dog timers, STK timerSo I will need a little prototyping board for each of the incoming chips:
CH32V002J4P6 - SOP8
CH32V002F4P6 - TSSOP20
CH32V006F8P6 - TSSOP20
CH32V006K8U6 - QFN32I’d also like to design a DIP8 adapter for the SOP8 package that would let me use these chips as a drop-in replacement for the Atmel AVR ATtiny13 that is in absolutely everything I sell. I have a bunch of 1:1 pin-mapping DIP8 adapters for the SOP8 packages. They’re handy for breadboarding.